Managing high-conflict cache lines in transactional memory computing environments
US9298626B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2013 |
| Grant date | Mar 29, 2016 |
| Priority date | — |
| Expiry date | Oct 24, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Cache lines in a computing environment with transactional memory are configurable with a coherency mode. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. When a transaction accessing a cache line in full-line coherency mode results in a transactional abort, the cache line may be placed in sub-line coherency mode if the cache line is a high-conflict cache line. The cache line may be associated with a counter in a conflict address detection table that is incremented whenever a transaction conflict is detected for the cache line. The cache line may be a high-conflict cache line when the counter satisfies a high-conflict criterion, such as reaching a threshold value. The cache line may be returned to full-line coherency mode when a reset criterion is satisfied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.