Method for forming a strained semiconductor structure
US9299563B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | Jun 24, 2014 |
| Grant date | Mar 29, 2016 |
| Priority date | — |
| Expiry date | Jun 24, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3065
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a method for forming a strained semiconductor structure. The method comprises providing a strain relaxed buffer layer, forming a sacrificial layer on the strain relaxed buffer layer, forming a shallow trench isolation structure through the sacrificial layer, removing at least a portion of an oxide layer on the sacrificial layer, etching through the sacrificial layer such that a portion of the strain relaxed buffer layer is exposed, forming the strained semiconductor structure on the exposed portion of the strain relaxed buffer layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.