High aspect ratio plasma etch for 3D NAND semiconductor applications
US9299580B2 · kind B2 · utility
14Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2014 |
| Grant date | Mar 29, 2016 |
| Priority date | — |
| Expiry date | Aug 19, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure provide methods for forming features in a film stack that may be utilized to form stair-like structures with accurate profiles control in manufacturing three dimensional (3D) stacking of semiconductor chips. In one example, a method of etching a material layer disposed on a substrate using synchronized RF pulses includes providing an etching gas mixture into a processing chamber having a film stack disposed on a substrate, synchronously pulsing a RF source power and a RF bias power into the etching gas mixture at a ratio of less than 0.5, and etching the film stack disposed on the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.