Implementing integrated circuit chip attach in three dimensional stack using vapor deposited solder Cu pillars
US9299591B1 · kind B1 · utility
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1Claims
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Key dates
| Filing date | Apr 28, 2015 |
| Grant date | Mar 29, 2016 |
| Priority date | — |
| Expiry date | Apr 28, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01029
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and structures are provided for implementing individual integrated circuit chip attach in a three dimensional (3D) stack. A plurality of hollow copper pillars is formed, and the hollow copper pillars are coated with lead free solder using vapor deposition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.