Methods for forming passivation protection for an interconnection structure
US9299605B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2014 |
| Grant date | Mar 29, 2016 |
| Priority date | — |
| Expiry date | May 2, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/321
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for forming a passivation protection structure on a metal line layer formed in an insulating material in an interconnection structure are provided. In one embodiment, a method for forming passivation protection on a metal line in an interconnection structure for semiconductor devices includes selectively forming a metal capping layer on a metal line bounded by a dielectric bulk insulating layer in an interconnection structure formed on a substrate in a processing chamber incorporated in a multi-chamber processing system, in-situ forming a barrier layer on the substrate in the processing chamber; wherein the barrier layer is a metal dielectric layer, and forming a dielectric capping layer on the barrier layer in the multi-chamber processing system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.