Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof
US9299670B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2013 |
| Grant date | Mar 29, 2016 |
| Priority date | — |
| Expiry date | Mar 14, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1461
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked microelectronic package can comprise a package body having an external vertical package sidewall, a plurality of microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the external vertical package sidewall. A cavity is formed on an external surface of the package body between a first one of the package edge conductors and a second one of the package edge conductors. Electrically conductive material is in the cavity and in electrical contact with a first and a second one of the package edge conductors, wherein the conductive material in the cavity is within planform dimensions of the microelectronic package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.