Fast-wake memory control
US9304579B2 · kind B2 · utility
16Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2015 |
| Grant date | Apr 5, 2016 |
| Priority date | — |
| Expiry date | Jul 13, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller is transitioned to a low-power mode in which an active-mode resource required to transmit memory access commands to a memory device at a first command-signaling frequency is disabled. The memory controller transmits a first memory access command to the memory device using an alternative signaling resource during a transitional interval in which the active-mode resource is re-enabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.