Patent · US Active

Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects

US9305878B2 · kind B2 · utility

1Cited by

20References

19Claims

0Family size

Assignee

GlobalFoundries Inc. · KY

Inventors

Torsten Huisinga · Dresden, DE
Carsten Peters · Dresden, DE
Andreas Ott · Erfurt, DE
Axel Preusse · Radebeul, DE

Key dates

Filing date	Dec 15, 2014
Grant date	Apr 5, 2016
Priority date	—
Expiry date	Dec 15, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a metal contact structure, an electrically conductive capping layer formed on the metal contact structure, and a conductive via electrically connected to the metal contact structure through the electrically conductive capping layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.