Devices and stacked microelectronic packages with package surface conductors and adjacent trenches and methods of their fabrication
US9305911B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2013 |
| Grant date | Apr 5, 2016 |
| Priority date | — |
| Expiry date | Dec 5, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1815
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of methods for forming microelectronic device packages include forming a trench on a surface of a package body in an area adjacent to where first and second package surface conductors will be (or have been) formed on both sides of the trench. The method also includes forming the first and second package surface conductors to electrically couple exposed ends of various combinations of device-to-edge conductors. The trench may be formed using laser cutting, drilling, sawing, etching, or another suitable technique. The package surface conductors may be formed by dispensing (e.g., coating, spraying, inkjet printing, aerosol jet printing, stencil printing, or needle dispensing) one or more conductive materials on the package body surface between the exposed ends of the device-to-edge conductors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.