Semiconductor devices having a silicon-germanium channel layer and methods of forming the same
US9305928B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2014 |
| Grant date | Apr 5, 2016 |
| Priority date | — |
| Expiry date | Jul 25, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/315
Abstract
Semiconductor devices having a silicon-germanium channel layer and methods of forming the semiconductor devices are provided. The methods may include forming a silicon-germanium channel layer on a substrate in a peripheral circuit region and sequentially forming a first insulating layer and a second insulating layer on the silicon-germanium channel layer. The methods may also include forming a conductive layer on the substrate, which includes a cell array region and the peripheral circuit region, and patterning the conductive layer to form a conductive line in the cell array region and a gate electrode in the peripheral circuit region. The first insulating layer may be formed at a first temperature and the second insulating layer may be formed at a second temperature higher than the first temperature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.