Memory cells
US9305929B1 · kind B1 · utility
52Cited by
9References
35Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2015 |
| Grant date | Apr 5, 2016 |
| Priority date | — |
| Expiry date | Feb 17, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/30
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.