Bottom recess process for an outer blocking dielectric layer inside a memory opening
US9305937B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2014 |
| Grant date | Apr 5, 2016 |
| Priority date | — |
| Expiry date | Oct 21, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
A method of minimizing an overetch or damage to a semiconductor surface underneath a memory opening is provided. A first blocking dielectric layer is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers. A sacrificial liner is formed over the first blocking dielectric layer. An opening is formed through a horizontal portion of the sacrificial liner. A horizontal portion of the first blocking dielectric layer at a bottom of the memory opening can be etched through the opening in the sacrificial liner. A semiconductor surface of the substrate can be physically exposed at a bottom of the memory opening with minimal overetch and/or surface damage. A second blocking dielectric layer can be formed, before or after formation of the sacrificial liner, to provide a multilayer blocking dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.