Semiconductor apparatus with multi-layer capacitance structure
US9305994B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2014 |
| Grant date | Apr 5, 2016 |
| Priority date | — |
| Expiry date | Sep 9, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/692
Abstract
A semiconductor apparatus including a stacked capacitance structure is provided. The stacked capacitance structure includes a first inner metal layer having a first pad area adjacent to an edge of the first inner metal layer, a first insulating layer disposed on the first inner metal layer and exposing the first pad area, a second inner metal layer disposed on the first insulating layer and having a second pad area adjacent to an edge of the second inner metal layer, a second insulating layer disposed on the second inner metal layer and exposing the second pad area, and a third inner metal layer covering the second inner metal layer and including at least one first slit. The first pad area and the second pad area include a plurality of pads. The first slit corresponds to the second pad area, such that the pads on the second pad area are exposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.