Accessing memory cells in parallel in a cross-point array
US9312005B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 10, 2013 |
| Grant date | Apr 12, 2016 |
| Priority date | — |
| Expiry date | May 23, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/77
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. The accessing in parallel is conducted while the cells are in a thresholded condition or while the cells are in a post-threshold recovery period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.