Storage in charge-trap memory structures using additional electrically-charged regions
US9312017B2 · kind B2 · utility
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14References
20Claims
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Key dates
| Filing date | Aug 12, 2014 |
| Grant date | Apr 12, 2016 |
| Priority date | — |
| Expiry date | Aug 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device includes a memory and a read/write (R/W) unit. The memory includes multiple gates coupled to a common charge-trap layer. The R/W unit is configured to program and read the memory by creating and reading a set of electrically-charged regions in the common charge-trap layer, wherein at least a given region in the set is not uniquely associated with any single one of the gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.