Maintenance operations in a DRAM
US9318183B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2015 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Nov 10, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4061
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.