Selective word line erase in 3D non-volatile memory
US9318206B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2014 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Nov 10, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/693
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An erase process for a 3D stacked memory device allows a portion of a block of memory cells to be erased. In one approach, in a U-shaped NAND string configuration, memory cells in the drain- or source-side columns are erased. In another approach, such as in a U-shaped or a straight NAND string configuration, memory cells in a portion of a column of memory cells are erased, and a dummy memory cell is provided between the erased and non-erased memory cells. A dummy memory cell can be on either side (e.g., above and below) of an erase memory cell, or on either side of a non-erased memory cell. A dummy memory cell is ineligible to store user data, but prevents a downshift in the threshold voltage of an erased memory cell from changing the threshold voltage of a non-erased memory cell, due to capacitive coupling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.