Memory device with secure test mode
US9318221B2 · kind B2 · utility
2Cited by
29References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2014 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | May 17, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method in a memory device that operates in a testing mode, includes receiving a vector to be written to the memory device. The vector is written to the memory device only if the vector belongs to a predefined set of test vectors. If the vector does not belong to the set of test vectors, the vector is converted to one of the test vectors, and the converted vector is written to the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.