Non-volatile memory structure employing high-k gate dielectric and metal gate
US9318336B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2011 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Aug 14, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A high dielectric constant (high-k) gate dielectric for a field effect transistor (FET) and a high-k tunnel dielectric for a non-volatile random access memory (NVRAM) device are simultaneously formed on a semiconductor substrate. A stack of at least one conductive material layer, a control gate dielectric layer, and a disposable material layer is subsequently deposited and lithographically patterned. A planarization dielectric layer is deposited and patterned, and disposable material portions are removed. A remaining portion of the control gate dielectric layer is preserved in the NVRAM device region, but is removed in the FET region. A conductive material is deposited in gate cavities to provide a control gate for the NVRAM device and a gate portion for the FET. Alternately, the control gate dielectric layer may replaced with a high-k control gate dielectric in the NVRAM device region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.