Semiconductor package and fabrication method thereof
US9318354B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2013 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Apr 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package is disclosed, which includes: a substrate having a plurality of switching pads, a plurality of first conductive pads and a plurality of circuits formed between the switching pads and the first conductive pads; an insulating layer covering the circuits; a conductive layer formed on the insulating layer and extending to the switching pads and the first conductive pads; and a semiconductor element disposed on the substrate and electrically connected to the switching pads through a plurality of bonding wires. By electrically connecting the switching pads and the first conductive pads through the conductive layer, the invention dispenses with the conventional short bonding wires so as to prevent the conventional problem of short circuits caused by contact of the short bonding wires with other bonding wires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.