Variable temperature solders for multi-chip module packaging and repackaging
US9318464B2 · kind B2 · utility
2Cited by
6References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 21, 2013 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Jun 8, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various methods of mounting semiconductor chips on a substrate are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a first plurality of solder interconnect structures to a first semiconductor chip. The first solder interconnect structures have a first melting point. The first semiconductor chip may be tested. If the first semiconductor chip passes the testing, then a second semiconductor chip is coupled to the first semiconductor chip using a second plurality of solder interconnect structures that have a second melting point lower than the first melting point.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.