Semiconductor structure and manufacturing method thereof
US9318490B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2014 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Aug 7, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0172
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a semiconductor structure, including a substrate, having a dielectric layer disposed thereon, a first device region and a second device region defined thereon, at least one first trench disposed in the substrate within the first device region, at least one second trench and at least one third trench disposed in the substrate within the second device region, a work function layer, disposed in the second trench and the third trench, wherein the work function layer partially covers the sidewall of the second trench, and entirely covers the sidewall of the third trench, and a first material layer, disposed in the second trench and the third trench, wherein the first material layer covers the work function layer disposed on partial sidewall of the second trench, and entirely covers the work function layer disposed on the sidewall of the third trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.