Layout configurations for integrating schottky contacts into a power transistor device
US9318597B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2013 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Oct 19, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/64
Abstract
A semiconductor device includes a vertical field-effect-transistor (FET) and a bypass diode. The vertical FET device includes a substrate, a drift layer formed over the substrate, a gate contact and a plurality of source contacts located on a first surface of the drift layer opposite the substrate, a drain contact located on a surface of the substrate opposite the drift layer, and a plurality of junction implants, each of the plurality of junction implants laterally separated from one another on the surface of the drift layer opposite the substrate and extending downward toward the substrate. Each of the one or more bypass diodes are formed by placing a Schottky metal contact on the first surface of the drift layer, such that each Schottky metal contact runs between two of the plurality of junction implants.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.