Method for fabricating a damascene self-aligned ferroelectric random access memory (F-RAM) having a ferroelectric capacitor aligned with a three dimensional transistor structure
US9318693B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2013 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Nov 15, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/22
Abstract
A method for a non-volatile, ferroelectric random access memory (F-RAM) device that includes a ferroelectric capacitor aligned with a preexisting structure is described. In one embodiment, the method includes forming an opening in an insulating layer over a contact in a planar surface of a substrate to expose at least a portion of the contact. Next a self-aligned contact (SAC) is formed electrically coupling to the contact, the SAC medially located in the opening and proximal to a sidewall thereof. A ferroelectric spacer is then formed in the opening medially of the SAC, and a top electrode spacer formed in the opening over the insulating cap and medially of the ferroelectric spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.