Dynamic cache and memory allocation for memory subsystems
US9323684B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2014 |
| Grant date | Apr 26, 2016 |
| Priority date | — |
| Expiry date | May 7, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technologies are presented that allow a portion of a cache to be used as a front memory when there is dynamic need based on system demand. A computing system may include at least one processor, a memory controlled by a controller and communicatively coupled with the at least one processor, a cache communicatively coupled with the at least one processor and the memory, and mapping logic communicatively coupled with the at least one processor, the memory, and the cache. The mapping logic may map a portion of the cache to a portion of the memory, wherein the portion of the cache is to be used by the at least one processor as a local memory, and wherein the mapping is dynamic based on system demand and managed by the controller in a physical address domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.