Antifuse OTP memory cell with performance improvement, and manufacturing method and operating method of memory
US9324381B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2015 |
| Grant date | Apr 26, 2016 |
| Priority date | — |
| Expiry date | Jan 27, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/64
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An OTP memory cell including an antifuse unit and a select transistor is provided. The antifuse unit includes an antifuse layer and an antifuse gate disposed on a substrate in sequence, a modified extension doped region disposed in the substrate below the antifuse layer, and a first doped region and a second doped region disposed in the substrate at two opposite sides of the antifuse gate. The select transistor includes a select gate, a gate dielectric layer, a second doped region, and a third doped region. The select gate is disposed on the substrate. The gate dielectric layer is disposed between the select gate and the substrate. The second and the third doped region are respectively disposed in the substrate at two opposite sides of the select gate. The doped region, the antifuse layer and the antifuse gate form a varactor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.