Memory device and operation method thereof
US9324428B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2015 |
| Grant date | Apr 26, 2016 |
| Priority date | — |
| Expiry date | Jun 2, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0092
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operation method for a memory device is disclosed. An operation state of the memory device is determined. If to be operated in a first operation state, the memory device is applied by a reset pulse. If to be operated in a second operation state, the memory device is applied by the reset pulse and at least a first incremental pulse set verification current, and an allowable maximum current of the first incremental pulse set verification current is lower than a melt current. If to be operated in a third operation state, the memory device is applied by the reset pulse and at least a first identical pulse set verification current, and an allowable maximum current of the first identical pulse set verification current is lower than the melt current. If to be operated in a fourth operation state, the memory device is applied by a set pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.