Weak erase after programming to improve data retention in charge-trapping memory
US9324439B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2014 |
| Grant date | Apr 26, 2016 |
| Priority date | — |
| Expiry date | Oct 20, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are provided to improve long term data retention in a charge-trapping memory device. In addition to a primary charge-trapping layer in which most charges are stored, the memory device may include a tunneling layer comprising an engineered tunneling barrier such as oxide-nitride-oxide. The nitride in the tunneling layer may also store some charges after programming. After the programming, a data retention operation is performed which de-traps some electrons from the tunneling layer, in addition to injecting holes into the tunneling layer which form neutral electron-hole dipoles in place of electrons. These mechanisms tend to lower threshold voltage. Additionally, the data retention operation redistributes the electrons and the holes inside the charge-trapping layer, resulting in an increase in threshold voltage which roughly cancels out the decrease when the data retention operation is optimized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.