Memory unit and method of testing the same
US9324453B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2014 |
| Grant date | Apr 26, 2016 |
| Priority date | — |
| Expiry date | Mar 21, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory unit that includes a tracking unit, a scan chain and a scan chain control unit. The tracking unit includes a tracking bit line, wherein the tracking unit is configured to receive a tracking control signal, selectively charge or discharge a voltage on the tracking bit line in response to the tracking control signal and generate a sense amplifier signal. The scan chain includes one or more logic devices, wherein the scan chain is configured to receive at least a first control signal. The scan chain control unit is connected to the scan chain and the tracking unit. The scan chain control unit is configured to receive the sense amplifier signal and generate the first scan chain control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.