Methods of forming elastically relaxed SiGe virtual substrates on bulk silicon
US9324617B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 18, 2015 |
| Grant date | Apr 26, 2016 |
| Priority date | — |
| Expiry date | May 18, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One method disclosed herein includes forming a virtual substrate by forming a sacrificial semiconductor material in a trench between a plurality of silicon fin structures formed in a bulk silicon substrate, forming a layer of silicon above the silicon fin structures and the sacrificial semiconductor material, performing at least one etching process to selectively remove the sacrificial semiconductor material relative to the silicon fin structures and the layer of silicon so as to define a cavity, forming a non-sacrificial semiconductor material on the layer of silicon and forming a layer of strained channel semiconductor material above the non-sacrificial semiconductor material positioned above the upper surface of the layer of silicon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.