Inventor · Saratoga Springs, NY, US

Murat Kerem Akarvardar

58Patents

10h-index

45Co-inventors

74Inventor score

Filing activity: May 31, 2013 → Jun 30, 2023

Most-cited inventions

Patent	Title	Area	Cited by	Status
US9343300B1	Methods of forming source/drain regions for a PMOS transistor device with a germanium-containing channel region	Electricity	24	Active
US9929157B1	Tall single-fin fin-type field effect transistor structures and methods	Electricity	21	Active
US9165837B1	Method to form defect free replacement fins by H2 anneal	Electricity	20	Active
US10217846B1	Vertical field effect transistor formation with critical dimension control	Electricity	14	Active
US9576857B1	Method and structure for SRB elastic relaxation	Electricity	11	Active
US9224865B2	FinFET with insulator under channel	Electricity	11	Active
US9117875B2	Methods of forming isolated germanium-containing fins for a FinFET semiconductor device	Electricity	11	Active
US9006077B2	Gate length independent silicon-on-nothing (SON) scheme for bulk FinFETs	Electricity	10	Active
US9252245B1	Spacer-last replacement metal gate flow and device	Electricity	10	Active
US9147616B1	Methods of forming isolated fins for a FinFET semiconductor device with alternative channel materials	Electricity	10	Active
US9385233B2	Bulk finFET with partial dielectric isolation featuring a punch-through stopping layer under the oxide	Electricity	9	Active
US9716174B2	Electrical isolation of FinFET active region by selective oxidation of sacrificial layer	Electricity	9	Active
US9324617B1	Methods of forming elastically relaxed SiGe virtual substrates on bulk silicon	Electricity	5	Active
US9245980B2	Methods of forming substantially defect-free, fully-strained silicon-germanium fins for a FinFET semiconductor device	Electricity	5	Active
US9293587B2	Forming embedded source and drain regions to prevent bottom leakage in a dielectrically isolated fin field effect transistor (FinFET) device	Electricity	5	Active
US10297597B2	Composite isolation structures for a fin-type field effect transistor	Electricity	4	Active
US9564486B2	Self-aligned dual-height isolation for bulk FinFET	Electricity	4	Active
US9362361B1	Methods of forming elastically relaxed SiGe virtual substrates on bulk silicon	Electricity	4	Active
US9324790B2	Self-aligned dual-height isolation for bulk FinFET	Electricity	4	Active
US8963259B2	Device isolation in finFET CMOS	Electricity	4	Active
US9589849B2	Methods of modulating strain in PFET and NFET FinFET semiconductor devices	Electricity	3	Active
US9530869B2	Methods of forming embedded source/drain regions on finFET devices	Electricity	3	Active
US9570588B2	Methods of forming transistor structures including forming channel material after formation processes to prevent damage to the channel material	Electricity	3	Active
US9287130B1	Method for single fin cuts using selective ion implants	Electricity	3	Active
US9601383B1	FinFET fabrication by forming isolation trenches prior to fin formation	Electricity	2	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.