Method of fabricating a memory structure
US9324724B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2015 |
| Grant date | Apr 26, 2016 |
| Priority date | — |
| Expiry date | Sep 21, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
Abstract
The present invention provides a method of fabricating a memory structure, especially forming an oxide on top of a spacer to prevent the spacer from being over-etched, the method comprising the steps of: providing a semiconductor substrate; forming a charge trapping layer, a first conducting layer and a capping layer as a gate stack on the substrate; forming a first gate structure by patterning; a plurality of spacers are patterned and disposed adjacent to the sidewall of said gate stack; depositing a second conducting layer on the substrate to cover the first gate structure and the spacer; selectively etching the second conducting layer to expose the top of the spacer; performing an oxidation process to form an oxide on top of the spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.