Structures and devices including a tensile-stressed silicon arsenic layer and methods of forming same
US9324811B2 · kind B2 · utility
480Cited by
551References
10Claims
0Family size
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Key dates
| Filing date | Sep 4, 2013 |
| Grant date | Apr 26, 2016 |
| Priority date | — |
| Expiry date | Sep 4, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/67207
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Structures including a tensile-stressed silicon arsenic layer, devices including the structures, and methods of forming the devices and structures are disclosed. Exemplary tensile-stressed silicon arsenic layer have an arsenic doping level of greater than 5 E+20 arsenic atoms per cubic centimeter. The structures can be used to form metal oxide semiconductor devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.