Gate dielectric protection for transistors
US9324822B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2014 |
| Grant date | Apr 26, 2016 |
| Priority date | — |
| Expiry date | Jul 1, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/393
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
At least one method, apparatus and system disclosed herein involves forming a device comprising a transistor comprising an active gate and at least one inactive gate in parallel to the active gate. A source region on a substrate is formed. An active gate region is formed on the substrate adjacent the source region. A drain region is formed on the substrate adjacent the active gate region. A first inactive gate region is formed on the substrate in parallel to the active gate region. The source region, the drain region, the active gate region, and the first inactive gate region comprise the transistor. The first inactive gate region is capable of dissipating the at least a portion of a charge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.