Suresh Uppal
12Patents
3h-index
15Co-inventors
46Inventor score
Filing activity: May 27, 2014 → Jan 26, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10106892B1 | Thermal oxide equivalent low temperature ALD oxide for dual purpose gate oxide and method for producing the same | Electricity | 402 | Active |
| US10181713B2 | Methods of post-process dispensation of plasma induced damage protection component | Electricity | 4 | Active |
| US9372226B2 | Wafer test structures and methods of providing wafer test structures | Electricity | 3 | Active |
| US9702926B2 | Methods, apparatus and system for screening process splits for technology development | Physics | 3 | Active |
| US10012687B2 | Methods, apparatus and system for TDDB testing | Physics | 2 | Active |
| US9460806B2 | Method for creating an OTPROM array possessing multi-bit capacity with TDDB stress reliability mechanism | Electricity | 1 | Active |
| US9916903B2 | OTPROM for post-process programming using selective breakdown | Electricity | 1 | Active |
| US9599656B2 | Methods, apparatus and system for voltage ramp testing | Physics | 1 | Active |
| US9500703B2 | Semiconductor structure having test device | Electricity | 0 | Active |
| US10054630B2 | Methods, apparatus and system for screening process splits for technology development | Physics | 0 | Active |
| US9324822B2 | Gate dielectric protection for transistors | Electricity | 0 | Active |
| US10147496B2 | OTPROM for post-process programming using selective breakdown | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.