System and method for micro-tiering in non-volatile memory
US9329804B2 · kind B2 · utility
6Cited by
5References
20Claims
0Family size
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Key dates
| Filing date | Jun 4, 2014 |
| Grant date | May 3, 2016 |
| Priority date | — |
| Expiry date | Jun 4, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0685
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a storage device such as a solid state disk (SSD), a central controller communicates with a plurality of multi-chip memory packages. Each multi-chip memory package comprises a plurality of memory dies and a local processor, wherein the plurality of memory dies includes different memory tiers. The central controller may handle management of the virtual address space while the local processor in each MCP manages the storage of data within memory tiers in the memory dies of its respective MCP.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.