Multi-core interconnect in a network processor
US9330002B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2011 |
| Grant date | May 3, 2016 |
| Priority date | — |
| Expiry date | Jun 29, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A network processor includes multiple processor cores for processing packet data. In order to provide the processor cores with access to a memory subsystem, an interconnect circuit directs communications between the processor cores and the L2 Cache and other memory devices. The processor cores are divided into several groups, each group sharing an individual bus, and the L2 Cache is divided into a number of banks, each bank having access to a separate bus. The interconnect circuit processes requests to store and retrieve data from the processor cores across multiple buses, and processes responses to return data from the cache banks. As a result, the network processor provides high-bandwidth memory access for multiple processor cores.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.