Bradley Dobbie
14Patents
3h-index
15Co-inventors
53Inventor score
Filing activity: Oct 28, 2011 → Mar 20, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9870328B2 | Managing buffered communication between cores | Physics | 6 | Active |
| US9501425B2 | Translation lookaside buffer management | Physics | 5 | Active |
| US9665505B2 | Managing buffered communication between sockets | Physics | 3 | Active |
| US9612934B2 | Network processor with distributed trace buffers | Physics | 2 | Active |
| US11119929B2 | Low latency inter-chip communication mechanism in multi-chip processing system | Physics | 2 | Active |
| US10331500B2 | Managing fairness for lock and unlock operations using operation prioritization | Physics | 1 | Active |
| US9330002B2 | Multi-core interconnect in a network processor | Physics | 1 | Active |
| US10248420B2 | Managing lock and unlock operations using active spinning | Physics | 0 | Active |
| US10599430B2 | Managing lock and unlock operations using operation prediction | Physics | 0 | Active |
| US11620223B2 | Low latency inter-chip communication mechanism in a multi-chip processing system | Physics | 0 | Active |
| US12019552B2 | Low latency inter-chip communication mechanism in a multi-chip processing system | Physics | 0 | Active |
| US10445096B2 | Managing lock and unlock operations using traffic prioritization | Physics | 0 | Active |
| US11327759B2 | Managing low-level instructions and core interactions in multi-core processors | Physics | 0 | Active |
| US11899967B2 | Vector processor data storage | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.