Patent · US Active

Clock region partitioning and clock routing

US9330220B1 · kind B1 · utility

2Cited by

15References

20Claims

0Family size

Assignee

XILINX, INC. · US

Inventors

Mehrdad Eslami Dehkordi · San Jose, US
Marvin Tom · Cupertino, US
Sridhar Krishnamurthy · San Jose, US
Abhishek Joshi · Seattle, US

Key dates

Filing date	Aug 25, 2014
Grant date	May 3, 2016
Priority date	—
Expiry date	Aug 25, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/331
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Clock region partitioning and clock routing includes creating partitions for a plurality of clocks of a circuit design, and legalizing the partitions using a processor according to a number of clocks in each partition and assignment of clock distribution tracks. Roots for implementing clock trees of the clocks are selected within the partitions.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.