Dynamic selection of output delay in a memory control device
US9330749B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2014 |
| Grant date | May 3, 2016 |
| Priority date | — |
| Expiry date | Nov 20, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an example, a memory control device includes an output circuit, an output delay unit, and a write-levelization controller. The output circuit is coupled to provide an output signal comprising a data signal or data strobe signal for a synchronous dynamic random access memory (SDRAM) system having a plurality of ranks. The output delay unit is coupled to apply an output delay to a bitstream to be transmitted to generate the output signal. The output delay includes an aggregate of a de-skew delay and a write-levelization delay. The write-levelization delay controller is coupled to adjust the write-levelization delay for each write transaction to the SDRAM system of a plurality of write transactions based on a selected rank of the plurality of ranks. The de-skew delay is the same across the plurality of ranks for each of the plurality of write transactions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.