Identifying word-line-to-substrate and word-line-to-word-line short-circuit events in a memory block
US9330783B1 · kind B1 · utility
14Cited by
30References
19Claims
0Family size
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Key dates
| Filing date | Dec 17, 2014 |
| Grant date | May 3, 2016 |
| Priority date | — |
| Expiry date | Dec 17, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a memory and a memory controller. The memory includes a memory block that includes memory cells connected by word lines. The memory controller is configured to store data in the memory cells, and to identify a suspected short-circuit event in the memory block by recognizing a deviation of a performance characteristic of at least a given word line in the memory block relative to the performance characteristic of remaining word lines in the memory block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.