Testing memory devices with distributed processing operations
US9330792B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2014 |
| Grant date | May 3, 2016 |
| Priority date | — |
| Expiry date | Jul 26, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/56008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Automated testing system and method of testing memory devices with distributed processing operations. A redundancy analysis system includes multiple test site processors (TSPs) respectively coupled to multiple devices under test (DUTs). Each TSP is installed with a redundancy analyzer configured to analyzing redundancy data returned from a respective (DUT). Each TSP may be coupled with a respective fail engine for returning the redundancy data from the corresponding DUT. A main TSP of the multiple TSPs is configured to control testing routine over the multiple DUTs and process failure related data from the DUTs. The main TSP may direct the RAs distributed in the multiple TSPs to execute the redundancy analyzers in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.