Through level vias and methods of formation thereof
US9330974B2 · kind B2 · utility
14Cited by
0References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2010 |
| Grant date | May 3, 2016 |
| Priority date | — |
| Expiry date | Feb 22, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a semiconductor device includes a first metal line disposed in a first metal level above a substrate. A second metal line is disposed in a second metal level disposed over the first metal level. A third metal line is disposed in a third metal level disposed over the second metal level. A through level via contacts the first metal line and the third metal line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.