Group III nitride integration with CMOS technology
US9331076B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2015 |
| Grant date | May 3, 2016 |
| Priority date | — |
| Expiry date | May 1, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/2015
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a structure that can be used to integrate Si-based devices, i.e., nFETs and pFETs, with Group III nitride-based devices is provided. The method includes providing a substrate containing an nFET device region, a pFET device region and a Group III nitride device region, wherein the substrate includes a topmost silicon layer and a <111> silicon layer located beneath the topmost silicon layer. Next, a trench is formed within the Group III nitride device region to expose a sub-surface of the <111> silicon layer. The trench is then partially filled with a Group III nitride base material, wherein the Group III nitride material base material has a topmost surface that is coplanar with, or below, a topmost surface of the topmost silicon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.