On-chip test for integrated AC coupling capacitors
US9335370B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2014 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | Oct 3, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/64
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Apparatus, method and computer program product for determining presence and relative magnitudes of on-chip AC coupling capacitors in a high-speed differential receiver device. A BIST method is employed to ultimately produce a dock count proportional to the fall time of a capacitor, and in the case of differential capacitors a difference in count values. Each capacitor path has a controllable first DAC current or voltage source. A second DAC current or voltage source, later in the data path and isolated from the capacitor node(s), is controlled to offset the voltage contribution of the charged and discharging capacitor. A count is recorded, starting when a capacitor charging current is shut off, and ends (the count) when the voltage of the charged capacitor falls below a threshold. A difference in count between the two data path capacitors is calculated and reported. A state machine operates the sequencing and control of the BIST.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.