Apparatus and methods for delay line testing
US9335372B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2013 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | Nov 5, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31703
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
This disclosure relates to delay line test circuits and methods. In one aspect, an integrated circuit (IC) can include a plurality of delay lines, a selection circuit, a delay comparison circuit, and a control circuit. The plurality of delay lines can generate a plurality of delayed clock signals, and the selection circuit can include a plurality of inputs configured to receive at least the plurality of delayed clock signals. The selection circuit can generate a first output clock signal and a second output clock signal by selecting amongst signals received at the plurality of inputs based on a state of a selection control signal. The delay comparison circuit can compare a delay of the first output clock signal to a delay of the second output clock signal and can generate a delay comparison such as a pass/fail flag based on the result. The control circuit can generate the selection control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.