Patent · US Active

Cache configured to log addresses of high-availability data via a non-blocking channel

US9336142B2 · kind B2 · utility

5Cited by

4References

13Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Sanjeev Ghai · Round Rock, US
Guy L. Guthrie · Austin, US
Hien Minh Le · San Jose, US
Hugh Shen · Round Rock, US
Philip G. Williams · Oakland, US

Key dates

Filing date	Nov 6, 2013
Grant date	May 10, 2016
Priority date	—
Expiry date	Jul 16, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG06F12/0811
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A technique for operating a data processing system includes determining whether a cache line that is to be victimized from a cache includes high availability (HA) data that has not been logged. In response determining that the cache line that is to be victimized from the cache includes HA data that has not been logged, an address for the HA data is written to an HA dirty address data structure, e.g., a dirty address table (DAT), in a first memory via a first non-blocking channel. The cache line that is victimized from the cache is written to a second memory via a second non-blocking channel.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.