Three-dimensional processing system having multiple caches that can be partitioned, conjoined, and managed according to more than one set of rules and/or configurations
US9336144B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jul 25, 2013 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | May 14, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Three-dimensional processing systems are provided which have multiple layers of conjoined chips, wherein one or more chip layers include processor cores that share cache hierarchies over multiple chip layers. The caches can be partitioned, conjoined, and managed according to various sets of rules and configurations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.