Common plate switching reduction in resistive switching memory devices
US9336868B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2013 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | Nov 2, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Structures and operations of a resistive switching memory device are described herein. In one embodiment, a resistive switching memory device can include: a plurality of resistive memory cells, each configured to be programmed to a low resistance state by application of a first voltage in a forward bias direction, and erased to a high resistance state by application of a second voltage in a reverse bias direction; a plurality of common plates, each being connected to a subset of the resistive memory cells; a command detector configured to detect a write command to be executed as a first and second write operations; and a write controller configured to perform the first write operation on each resistive memory cell in a selected subset, and to perform the second write operation on at least one of the resistive memory cells in the selected subset based on the detected write command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.