Package for three dimensional integrated circuit
US9337063B2 · kind B2 · utility
7Cited by
59References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2014 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | Jul 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.